hd6417727f160cv

Product Summary

The hd6417727f160cv is a single-chip RISC microprocessor that integrates a 32-bit RISC-type SuperH RISC engine architecture CPU with digital signal processing (DSP) extension as its core that has a cache memory, an on-chip X/Y memory, and a memory management unit (MMU) as well as peripheral functions required for system configuration. The hd6417727f160cv includes data protection, virtual memory, and other functions provided by incorporating an MMU into a SuperH Series microprocessor (SH-1 or SH-2). The hd6417727f160cv chip has the on-chip X/Y memory with large capacitance, on-chip DSP module, and emulator support.

Parametrics

hd6417727f160cv absolute maximum ratings: (1)Power supply voltage (I/O):–0.3 to 4.2V; (2)Power supply voltage (internal):–0.3 to 2.5V; (3)Input voltage (except port L):–0.3 to VccQ + 0.3V; (4)Input voltage (port L):–0.3 to AVcc + 0.3V; (5)Analog power-supply voltage:–0.3 to 4.6V; (6)USB power-supply voltage:–0.3 to 4.2V; (7)Analog input voltage:–0.3 to AVcc + 0.3V; (8)Operating temperature:–20 to 75℃; (9)Storage temperature:–55 to 125℃.

Features

hd6417727f160cv features: (1)Original Renesas SuperH architecture; (2)Object code level compatible with SH-1, SH-2 and SH-3; (3)32-bit internal data bus; (4)Sixteen 32-bit general registers (eight 32-bit shadow registers) ; (5)Eight 32-bit control registers; (6)Four 32-bit system registers; (7)Instruction length: 16-bit fixed length to improve code efficiency; (8)Load-store architecture; (9)Delayed branch instructions; (10)Instruction set based on C language; (11)Instruction execution time: one instruction/cycle for basic instructions ; (12)Logical address space: 4 Gbytes; (13)Space identifier ASID: 8 bits, 256 logical address space; (14)Five-stage pipeline; (15)Mixture of 16-bit and 32-bit instructions ; (16)32-/40-bit internal data bus ; (17)Multiplier, ALU, barrel shifter and DSP register; (18)Max. four parallel operations: ALU, multiply and two load or store ; (19)Two addressing units to generate addresses for two memory access ; (20)DSP data addressing modes: increment, indexing (with or without modulo addressing); (21)Zero overhead repeat loop control; (22)Conditional execution instructions; (23)User-DSP mode and privileged-DSP mode.

Diagrams